约翰逊计数器(扭环计数器).pptx

约翰逊计数器————Verilog语言module Johnson_4_1s(clk,rest,Q); //主模块，四个D触发器和一input clk; //个秒脉冲模块组成input rest;output [3:0]Q;wire [3:0]d;wire a;assign d[0]=Q[1];assign d[1]=Q[2];assign d[2]=Q[3];assign d[3]=~Q[0]|~Q[1]Q[2];D_FF dff0(rest,a,d[0],Q[0]);D_FF dff1(rest,a,d[1],Q[1]);D_FF dff2(rest,a,d[2],Q[2]);D_FF dff3(rest,a,d[3],Q[3]);cp_1s cp1(rest,clk,a);endmodulemodule D_FF(rest,clk,d,q); //D触发器模块input rest;input clk;input d;output q;reg q;always@(posedge rest or posedge clk)if(rest==1b1)beginq=1b0;endelsebeginq=d;endendmodulemodule cp_1s(rest,clk,a); //秒脉冲模块，输出a为一秒的脉冲input rest;input clk;output reg a; reg [25:0]q;always@(posedge clk or posedge rest) begin if(rest==1) begin q=0; a=0; end else if(q= begin q=0; a=~a; end else q=q+1; endendmoduleNET “Q[0]” LOC = M5; //管脚配置NET Q[1] LOC = M11;NET Q[2] LOC = P7;NET Q[3] LOC = P6;NET clk LOC = B8;NET rest LOC = P11;