标准单元包的低漏功耗设计和研究【毕业论文】.doc

- PAGE I - 本科毕业设计 （20 届） 标准单元包的低漏功耗设计和研究 所在学院 专业班级 电子信息科学与技术 学生姓名 学号 指导教师 职称 完成日期 年 月 PAGE I 摘　要 【摘要】随着工艺特征尺寸进入纳米时代，集成电路在设计和制造上出现了新的挑战——功耗。功耗随工艺特征尺寸减小不断上升，尤其是漏功耗呈现指数形式上升。为了降低漏功耗，本文针对ASIC（Application Specific Integrated Circuit，专用集成电路）半定制设计，提出了一种基于标准单元包的沟道长度调制技术。在130nm工艺下，本文对反相器、与非门和或非门标准单元进行沟长调制；然后使用HSPICE进行电路仿真，得出了沟道长度最优值；最后制成新的标准单元，并扩展标准单元包。实验结果表明，沟长调制方法效果明显，调制后标准单元的漏功耗与Smic130nm工艺的标准单元相比降低了34%—60%。 【关键词】标准单元；漏功耗；ASIC；沟长调制 Abstract 【ABSTRACT】With the technology of integrated circuit design stepping into nanometer era, power has become one of the most critical concerns. The feature size of integrated circuit has reduced continually, which leads to exponential power-rise, especially leakage power. In order to reduce leakage power, a gate-length biasing design methodology based on the standard cells of ASIC (Application Specific Integrated Circuit) semicustom design methodology is proposed in this brief. At 130nm technology, author biased the gate-length of existing INVERTER, NAND and NOR standard cells, then got the suitable gate-length sizes by HSPICE simulation and result analysis. Finally new gate-length biased standard cells using these sizes were designed and they were added into ASIC standard library. Experimental result shows that gate-length biased cells can decrease leakage power by 34%－60% compared with Smic-130nm standard cells. 【KEYWORDS】standard cells；leakage power；ASIC；gate-length biasing 目　录 TOC \o 1-3 \h \z \u HYPERLINK \l _Toc293782454 摘　要 PAGEREF _Toc293782454 \h II HYPERLINK \l _Toc293782455 Abstract PAGEREF _Toc293782455 \h III HYPERLINK \l _Toc293782456 目　录 PAGEREF _Toc293782456 \h IV HYPERLINK \l _Toc293782457 1 引 言 PAGEREF _Toc293782457 \h 1 HYPERLINK \l _Toc293782458 1.1 集成电路的发展概况 PAGEREF _Toc293782458 \h 1 HYPERLINK \l _Toc293782459 1.2 低漏功耗研究的意义 PAGEREF _Toc293782459 \h 1 HYPERLINK \l _Toc293782460 1.3 基于ASIC