Quartus II 时序约束方法.ppt

* These undefined clocks could be purposefully or accidentally created. For example, a “clock” could have been created due to incorrect HDL coding. * * Now we are going to check what SDC timing constraints we would apply to the following design situations. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Now we are going to fo through most of the paths you will have in your design and see check what SDC timing constraints we would apply to these situations. * Clocks are not actual physical locations in the design. They represent signal characteristics applied to a point in the design. Virtual clocks would be used, for example, if you are driving data off chip to an external device running on a different clock. You can specify the I/O timing in relation to that external clock, so that you can analyze timing between your design and the other device. If you only constrained only your clocks, then all internal logic would in effect be constrained. I/O require more information. The complexity of the design would determine how well simple con * * * * * Ex. 1 – Port clk_in has a clock applied to it named clk_50 that has a period of 20 ns. Ex. 2 – Port sysclk has a clock applied to it named sysclk that has a period of 10 ns, but a duty cycle of 60%. * * * * * * * * * * * * * * Use early and late to indicate maximum and minimum PCB propagation delay times. * * * * * * * * * * * * * * * * * * Truly asynchronous paths cannot be analyzed for timing * * Speaker Note: “no sep model for rise / fall means that the slower is defined for slow corner model then the fast model (for stratix is defined by scaling that model. This means that the actual fastest path (rise or fall) may not be captured. Guardbanding is very important to catch this. * * * This section is provided as a quick review. The idea is that the students have already attended the Quartus II training showing how to use TimeQuest. If they have not, then you can refer to the detailed slides in th