基于终端电容复用开关策略的11位逐次逼近型ADC的研究与设计-电路与系统专业论文.docxVIP

浙江大学硕士学位论文 浙江大学硕士学位论文 摘要 摘要 逐次逼近型模数转换器(SARADC)因其功耗低、面积小等特点，长期以来获 得了广泛的应用。近年来，随着CMOS器件特征尺寸的不断减小和速度的提高， SAR ADC已可实现高达12位的精度和10MS／s或更高的转换速率，有望在医 疗电子产品例如植入式芯片等低功耗高精度微型化的集成电路系统中获得广泛 应用。因此，低功耗SARADC的设计技术日益受到关注。 论文提出了一种11位5MS／s的低功耗SAR ADC的设计，采用电荷再分配 型DAC、动态比较器、异步时钟控制和寄存器电路实现。其特点是在对现有的 开关切换策略进行对比的基础上，分析了开关切换策略对DAC动态功耗和非线 性参数INL／DNL的影响，提出了一种终端电容复用的开关切换策略，从而大幅 度优化了电荷再分配型DAC模块的动态功耗和面积。系统采用异步时钟控制， 避免使用高频时钟产生器，同时采用片外可调电阻调节控制信号延时，使得ADC 可以在多种转换速率下工作并充分利用转换相位的时间，降低对比较器速度的要 求。 系统采用SMIC 0．18urn混合信号工艺设计完成并付诸流片，仿真结果表明 SNDR为55．1dB，SFDR为68．38dB，功耗为0．236mW，验证了本文提出的开关 切换策略。 关键词：模数转换器；逐次逼近型；开关切换策略；终端电容复用；异步时钟 n 浙江大学硕士学位论文 浙江大学硕士学位论文 Abstraet Abstract For quite a long time，successive approximation register analog-to-digital converter(SAR ADC)has got extensive applications since it features low power dissipation and small chip area．In recent years，硒the continuous shrink of CMOS device feature size and the increase of its speed,all SAR ADC、析tll several tens of MS／s sampling rates and up to 1 2一bit resolution is achievable，which makes them show a great potential to apply to low power high performance integrated systems such孙medical electronics products especially that uses implantable biomedical devices，etc． In this thesis，a low power 1 1-bit 5-MSamples／s SAR ADC was proposed．It consists of a charge-redistribution DAC，a dynamic comparator,together诵t11 asynchronous clock control circuits and registers．The rde蛐ight of the work is that based on analysis of the influence of the switching procedure on dynamic power dissipation of capacitive DAC and nonlinearity parameters INL／DNL，a novel switching procedure named Terminating Capacitor Reused procedure Was put forward，which results in reducing dynamic power dissipation and chip area．Here the traditional high-frequency clock generator is replaced by asynchronous control logic circuits to reduce design complexity．In addition,bY u