EDA技术与应用讲义 第2章 EDA设计流程及其工具.pptVIP

Timing SNF Extractor(时序SNF文件提取器) The Compiler module that creates a timing SNF containing the logic and timing information required for timing simulation, delay prediction, and timing analysis. The Timing SNF Extractor is turned on with the Timing SNF Extractor command (Processing menu). It is also turned on automatically when you turn on the EDIF Netlist Writer, Verilog Netlist Writer, or VHDL Netlist Writer command (Interfaces menu). The Timing SNF Extractor cannot be turned on at the same time as the Functional SNF Extractor or the Linked SNF Extractor. A timing SNF describes the fully optimized circuit after all logic synthesis and fitting have been completed. Regardless of whether a project is partitioned into multiple devices, the timing SNF describes a project as a whole. Therefore, timing simulation and timing analysis (including delay prediction) are available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional testing is available only for a single-device project. 返回 Assembler（汇编器） The Compiler module that creates one or more programming files for programming or configuring the device(s) for a project. The Assembler module completes project processing by converting the Fitters device, logic cell, and pin assignments into a programming image for the device(s), in the form of one or more POFs, SOFs, Hex Files, TTFs, Jam Files, JBC Files, and/or JEDEC Files. POFs and JEDEC Files are always generated; SOFs, Hex Files, and TTFs are always generated if the project uses ACEX 1K, FLEX 6000, FLEX 8000 or FLEX 10K devices; and Jam Files and JBC Files are always generated for MAX 9000, MAX 7000B, MAX 7000AE or MAX 3000A projects. If you turn on the Enable JTAG Support option in the Classic MAX Global Project Device Options dialog box (Assign menu) or the Classic MAX Individual Device Options dialog box, the Assembler will also generate Jam Files and JBC Fi