用VHD设计键盘输入显示方案.docVIP

1、显示控制 -- Module Name: DispCtrl - Behavioral -- Description: Generates the immage for the VGA Demo -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DispCtrl is Port (clk25MHz : in std_logic; Hcnt: in std_logic_vector(9 downto 0); -- horizontal counter Vcnt: in std_logic_vector(9 downto 0); -- verical counter romdatain : in std_logic_vector(7 downto 0); -- vvvvvvvvvvvvvvvvvvv outRed : out std_logic_vector(2 downto 0); -- final color outGreen: out std_logic_vector(2 downto 0); -- outputs outBlue : out std_logic_vector(1 downto 0); adrVideoMem : out std_logic_vector(3 downto 0)); -- addr in the Logo immage end DispCtrl; architecture Behavioral of DispCtrl is -- constants for Synchro module constant PAL:integer:=640; --Pixels/Active Line (pixels) constant LAF:integer:=480; --Lines/Active Frame (lines) -- constants for VGA Demo constant HBorder:integer:=40; -- Horizontal border (pixels) constant VBorder:integer:=40; -- Vertical border (lines) constant Hsize:integer:=7; -- Horizontal logo size (pixels) 标志的水平尺寸 64 constant Vsize:integer:=11; -- Vertical logo size (pixels) 标志的垂直尺寸 64 signal Horigin:integer:=60; -- Horizontal logo origin (pixels) 标志的水平原点 signal Vorigin:integer:=60; -- Vertical logo origin (pixels) 标志的垂直原点 signal adrVideoPixel: std_logic_vector(2 downto 0); signal adrVideoLine: std_logic_vector(3 downto 0); signal cntDyn: integer range 0 to 2**28-1; -- dynamic effect counter signal intHcnt: integer range 0 to 800-1; --PLD-1 - horizontal counter--- 水平计数器 signal intVcnt: integer range 0 to 521-1; -- LFD-1 - verical counter --- 垂直计数器 begin -- mapping the std_logic_vector ports to internal integers intHcnt = conv_integer(Hcnt); intVcnt = conv_integer(Vcnt); adrVideoPixel = co