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ABSTRACT
CMOS image sensor (CIS) system on chip, as the main source of image information collection unit, have a wide range of applications in the aerospace and defense fields, so its radiation-tolerant ability is essential. Image signal processing circuit is an important part of CIS system on chip, and we have to improve its radiation hardened capability. The cost of SOI integrated circuit foundry is very expensive, and using the commercial technology to improve radiation-hardened performance of ICs through the design methods is becoming the hotspot in the field. In order to consume less hardware resources and achieve better processing and radiation-hardened ability, the design of radiation-tolerant image signal processing circuit has become a major challenge.
For the above, this paper analyzes the mechanism of ICs in the radiation environment, including total dose radiation and single-ion irradiation. For the different types of irradiation, image signal processing circuit has been reinforced design and researched on transistor-level, unit-level and layout-level. According to the general characteristics of current image sensor and image signal processor, the main algorithms of pipeline-structure image signal processing circuit, such as lens correction, color interpolation, auto-white balance, color space conversion, gamma correction and contrast adjustment, have been studied and implemented by Verilog HDL code. At the same time, the function of Verilog Code has been verified. Finally, based on full custom ASIC library, the code of radiation-hardened image signal processing circuit has been synthesized and the layout has been achieved.
The size of the input Bayer format image is up to 752 × 582, and the frame rate is up to 30fps. The input data width is 10bit, and the output data after processing is the 16bit-width YCbYCr compression format. The frequecy of the system clock is 20MHz,
and the power dissipation of the circuit is 77.36mW, the area is 1865671μm2 and th
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