天津大学计算机系统结构课件 第二章 课件1.pptVIP

William Stallings Computer Organization and Architecture Chapter 2Computer Evolution and Performance Topics History of Computers 计算机简史 Designing for Performance 性能设计 Pentium Evolution 奔腾芯片的进展 Performance Measurement 性能测量方法 The first Generation: Vacuum Tubes真空管 ENIAC - background Electronic Numerical Integrator And Computer电子数字积分器和计算机 Eckert and Mauchly 埃克特和莫克利 University of Pennsylvania Trajectory tables for weapons Started 1943 Finished 1946 Too late for war effort (Quiz: When did WWII end?) Used until 1955 ENIAC – details (It’s BIG) Decimal (not binary) 采用十进制表示/运算 20 accumulators of 10 digits 20个10位累加器 Programmed manually by switches 设置开关手工编程 18,000 vacuum tubes 真空管 70,000 resistors 电阻 10,000 capacitors 电容 6,000 switches 开关 30 tons 15,000 square feet 140 KW power consumption 5,000 additions per second von Neumann/Turing冯诺依曼/图灵 Stored Program concept Main memory storing programs and data主存储器：用于存储数据和指令 ALU operating on binary data能够操作二进制数的算术逻辑单元 Control unit interpreting instructions from memory and executing控制器：翻译内存中的指令并执行 Input and output equipment operated by control unit由控制器操纵的输入、输出设备 von Neumann/Turing 存储程序思想：将事先编好的程序和原始数据送入主存中，然后启动计算机工作。计算机应能在不需操作人员干预下，自动完成逐条取出指令和执行指令的任务。 Princeton Institute for Advanced Studies 普林斯顿高级研究院, 1946 IAS Completed 1952:Basis for virtually every machine designed since then 是后来通用计算机的原型 Structure of von Nuemann machine IAS details --- memory 1000 x 40 bit words （figure 2.2） Binary number 2 x 20 bit instructions IAS – von Neumann Architecture Features Data and instructions are stored in a single R/W memory 数据和指令使用同一个读写存储器 Memory contents are addressable by location, regardless of the content存储器内容根据地址访问 Sequential execution顺序执行 IAS – von Neumann Architecture Set of registers (storage in CPU) Memory Buffer Register(MBR) 存储缓冲寄存器 Memory Address Register(MAR) 存储地址寄存器 Instruction Register(IR) 指令寄存器 Instruction Buffer Register(IBR) 指令缓冲寄存器 Program Counter(PC) 程序计数器 Accumulator(AC) 累加器 Multiplier Quotient乘商寄存器(M