射频宽带分频器的研究与设计-电子科学与技术；电路与系统专业毕业论文.docxVIP

东南大学硕士 学价论文 II 万方数据 AbstractAb Abstract Ab stract With the high—speed development of the wireless communication systems and other relevant fields，more wireless communication standard protocols have been widely used，resulting that research and design of multi—mode communication chips have attracted more and more attention． In multi—mode communication system，a difficulty of this circuit is the design of the frequency synthesizer(FS)，which enables tO provide high—accuracy and high—stabilization signals as the standard reference frequency．In phase—locked—loop(PLL)based FS，the frequency divider is one of the most important blocks，which makes FS possible to provide high-precision frequency signals while reaching high operating frequency and low power consumption． Firstly,we summarize the principle of the PLL—based FS and how it works，and analyze its linear model briefly．Secondly，a comprehensive summary and comparisons of frequency dividers are presented，which includes various structures of triggers and their merits and drawbacks in performance．Then，this thesis mainly describes a programmable divider based on the pulse—swallow counter and a multi-modulus divider based on cascaded divide—by一213 cells， including the operating principles and basic structures． Used in L-band multimode wireless communication receiver,this thesis presents a design of programmable divider baesd on the pulse—swallow counter in 0．1 8一gm CMOS process。including its pre-simulation，layout and post—simulation．Its modulus can be varied from 128 to 5 1 1．The post simulation shows that the programmable divider can operate well over a wide range of 2-4 GHz．The core circuit without test buffers consumes 3．69 mA current from a 1．8 V power supply and occupies a chip area of approximately 0．0 1 82 mm2． Finally,the high-speed multi—modulus divider is designed based on cascaded divided—by一2／3 cells in 90rim CMOS，the modulus of which can be varied from 1 6 to 3 1．The post simulation shows that the programmable div