基于FPGA的Verilog语言描述的SDRAM存储器接口设计学士学位论文.docVIP

PAGE II - - - PAGE VI - 毕业论文 基于EPM570的SDRAM存储器接口实现 摘 要 随着信息科学的飞速发展，人们面临的信号处理任务越来越繁重，对数据采集处理系统的要求也越来越高。单片机、DSP等微处理器内部RAM有限，这就需要在微处理器的外部扩展存储器。同步动态随机访问存储器具有价格低廉、密度高、数据读写速度快的优点，从而成为数据缓存的首选存储介质，在数据采集系统和图像处理系统等方面中有着重要和广泛的应用。 SDRAM 的读写逻辑复杂，最高时钟频率达100MHz 以上，普通单片机无法实现复杂的SDRAM 控制操作。复杂可编程逻辑器件CPLD具有编程方便，集成度高，速度快，价格低等优点。因此选用 CPLD 设计SDRAM 接口控制模块, 简化主机对SDRAM 的读写控制。通过设计基于CPLD 的SDRAM 控制器接口，可以在STM系列、ARM系列、STC系列等单片机和DSP等微处理器的外部连接SDRAM，增加系统的存储空间。 论文开始介绍了SDRAM接口设计研究的背景和研究的目的及意义，引出对SDRAM的研究，详细介绍了SDRAM的基本原理、内部结构、基本操作和工作时序，以及设计的重点及难点。在这些理论基础上对SDRAM接口进行模块化设计，了解设计中所使用的硬件和软件。最后用Verilog语言在软件QuartusⅡ设计CPLD芯片，通过在硬件和软件上的调试基本实现了SDRAM接口的设计。 关键词　SDRAM；接口；Verilog；CPLD The Implementation of SDRAM Memory Interface Based on the EPM570 Abstract With the rapid development of information science, people face more and more onerous task of signal processing, the requirements of data acquisition and processing system are getting higher and higher. Microprocessor such as single-chip microprocessor, DSP etc, their RAM is limited, which requires external expansion in the microprocessor memory. Synchronous Dynamic Random Access Memory has a low cost, high density, fast read and write data on the merits, thereby becoming the first choice for data cache storage medium, which paly an important role and widely used in the data acquisition system and image processing systems. SDRAM read and write logic is complex, the maximum clock frequency reaches above 100MHz, the ordinary microcontroller can not achieve complex SDRAM control operation. Complex programmable logic device has advantages such as programming convenience, high integrity, high speed and low cost etc. Therefore select CPLD to design control module of SDRAM interface , to simplify the host to read and write control of the SDRAM. Through the design of SDRAM controller interface based on CPLD, you can connect SDRAM in the external of STM series, ARM series, STC series single chip microprocessor and the DSP, increase system storage space. At the begi