快速以太网物理层中低压高速模数转换器设计研究-软件工程专业论文.docxVIP

摘 摘 要 万方数据 万方数据 万方数据 万方数据 摘 要 在快速以太网的物理层中，数据接收通路需要一个采样速率为 125MHz、分 辨率为 8 比特的模数转换器将从 5 类非屏蔽双绞线上接收到的 MLT_3 码信号转 换为数字信号，以供后端数字电路模块进行编解码、数据串并转换以及时钟数据 恢复等。在综合考虑模数转换器的采样速率和分辨率两个重要参数以后，本论文 中的模数转换器采用了具有高速、中高等精度、结构相对简单等特点的流水线结 构。 基于快速以太网接收器的应用背景，本论文设计了数据接收通路中转换速率 为 125MHz、分辨率为 8 比特的流水线模数转换器。设计中采用了双采样、两级 运放的电流缓冲式密勒补偿等关键技术，分析了传统流水线模数转换器的非理想 性，介绍了数字校准技术、带隙基准电路和参考源缓冲器等电路模块。流水线模 数转换器的设计采用了 SMIC 0.13um CMOS 工艺，差分输入满摆幅为 1Vpp，当 输入信号频率为 1MHz、采样频率为 125MHz 时，流水线 ADC 的微分非线性误差 DNL 峰值为+0.28LSB/-0.18LSB，积分非线性误差 INL 峰值为+0.25LSB/-0.41LSB， 信号噪声比（SNR）为 48.2dB，信号噪声失真比（SNDR）为 48.0dB，有效位数 约合为 7.70 位，能够满足以太网系统对模数转换器性能的要求。 关键词：快速以太网 流水线模数转换器 双采样技术 电流缓冲式密勒补偿 Abst Abstract 万方数据 万方数据 万方数据 万方数据 Abstract In Fast Ethernet physical layer, the data receiving path requires a ADC, whose sampling rate is 125MHz, and has a resolution of 8-bit, to convert MLT_3 code signal that is received from the 5 unshielded twisted pair into digital signal, which will be encoded and decoded in the back-end digital module, so that the clock and data can be recovered. In consideration of the two important parameters: sampling rate and resolution of ADC, this paper designed a pipeline ADC whose advantages are high-speed medium-precision and simple structure. Based on the background of Fast Ethernet Receiver application, this paper realizes an pipeline ADC which has 125MHz sampling rate and 8-bit resolution. In receive data path, the key technologies are Double Sampling and current buffered Miller compensation. This paper analyzes the imperfection of the traditional pipeline ADC, introduces a digital calibration technique, the bandgap reference circuit and voltage reference buffer. Pipelined ADC was designed using SMIC 0.13um CMOS process, the differential input full swing is 1Vpp, when the input signal frequency is 1MHz and the sampling frequency is 125MHz, the peak value of differential nonlinearity error DNL is +0.28 LSB/-0.18LSB, the peak value of integral nonlinearity INL is +0.25 LSB/-0.41LSB, signal to noise ratio (SNR)