VHDL与数字集成电路设计VHDL7-1.pptVIP

* * * 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width Local clocks can be gated “off” to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking trise = 0.35ns tskew = 50ps tcycle= 1.67ns EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS Global clock waveform * * * Two Phase Handshake * EE141 * EE141 * * * D Clk Q D Q Clk tc-q thold PWm tsu td-q Delays can be different for rising and falling data transitions T * D Clk Q D Q Clk tc-q thold T tsu Delays can be different for rising and falling data transitions * Sources of clock uncertainty * Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking * Both skew and jitter affect the effective cycle time Only skew affects the race margin Clk Clk tSK tJS * * Launching edge arrives before the receiving edge * Receiving edge arrives before the launching edge * Minimum cycle time: T - ? = tc-q + tsu + tlogic Worst case is when receiving edge arrives early (positive ?) * Hold time constraint: t(c-q, cd) + t(logic, cd) thold + ? Worst case is when receiving edge arrives lateRace between data and clock * * Clk T TSU TClk-Q TLM Latest point of launching Earliest arrivalof next cycle TJI + d * If launching edge is late and receiving edge is early, the data will not be too late if: Minimum cycle time is determined by the maximum delays through the logic Tc-q + TLM + TSU T – TJI,1 – TJI,2 - d Tc-q + TLM + TSU + d + 2 TJI T Skew can be either positive or negative * Clk TClk-Q TLm Earliest point of launching Data must not arrivebefore this time Clk TH Nominalclock edge * Minimum logic delay If launching edge is early and receiving edge is late: Tc-q + TLM – TJI,1 TH + TJI,2 + d Tc-q + TLM