时序电路VHDL设计(时序逻辑部分).pptVIP

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY sqs IS PORT( Rst,x,clk: in Std_logic; z: out Std_logic); END sqs; ARCHITECTURE a OF mealy IS TYPE STATE_TYPE IS (s0, s1, s2); SIGNAL state: STATE_TYPE; BEGIN PROCESS (rst,clk) BEGIN If (Rst=‘1’) then state=s0; elsif （clk‘EVENT AND clk = ’1‘） then CASE state IS WHEN s0 = IF din=‘1’ THEN state = s1; else state=s0; END IF; WHEN s1 = IF din=‘1 THEN state = s2; else state=s0; END I