数字VLSI电路测试技术研究-VASTlabatUCLA.PPT

Outline Brief Introduction to ICT, CAS RD in Test Verification Impact China Test Community (CCF) On-going… US Government Reports (1/2) US Government Reports (2/2) 龙芯CPU芯片1号,2号系列-核 龙芯1号：32位通用处理器芯片 0.18微米工艺 32位 0.4瓦@266MHz 面积3.8mm*3.8mm 龙芯CPU芯片3号系列-多核 单结点4个四发射64位处理器核 65nm工艺设计，集成HT 1.0高速IO接口、DDR2/3高速内存控制器，功耗10瓦，主频1GHz Advanced Test Technology Lab. 团队的发展得益于973项目资助 团队的成长受益于NSFC持续资助 团队的成长受益于NSFC持续资助 Outline Brief Introduction to ICT, CAS RD in Test Verification Impact China Test Community (CCF) On-going… Selected papers in test compression Jie Dong, Yu Hu, Yinhe Han, Xiaowei Li, “An On-chip Combinational Decompressor for Reducing Test Data Volume”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS’06), May 21-24, 2006, Greece, pp.1459-1462 Yu Hu, Yinhe Han, Xiaowei Li, “Compression/Scan Co-Design to Reduce Test Data Volume, Scan-in Power Dissipation and Test Application Time”, Proc. of IEEE Pacific-Rim Dependable Computing (PRDC), Dec.12-14, 2005, Changsha, pp.175-182 Yinhe Han, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra, Xiaowei Li, “Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor”, Proc. of IEEE Asian Test Symposium (ATS), Dec.17-21, 2005, Kolkata, India, pp.373-377 Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, “Theoretic Analysis and Enhanced X-Tolerance of Test Response Compact based on Convolutional code”, Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 18-21, 2005, Shanghai, pp.53-58 Best Paper Candidate Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, and Anshuman Chandra, “Test Resource Partitioning Based on Efficient Responses Compaction for Test Time and Test Channels Reduction”, Proc. of IEEE Asian Test Symp. (ATS’03), Nov. 16-19, 2003, Xi’an, pp.440-445 Best Paper Award Selected papers in delay (fault) testing Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path correlations”, Proc. of IEEE VLSI Test Symposium (VTS),