JPEG2000中DWT-EBCOT联合的高效低存储VLSI结构.pdfVIP

第 31 卷第 3 期 电 子 与 信 息 学 报 Vol.31No.3 2009 年 3 月 Journal of Electronics Information Technology Mar.2009 JPEG2000 中DWT-EBCOT 联合的高效低存储 VLSI 结构 郭 杰 李云松 吴成柯 刘 凯 王柯俨 (西安电子科技大学综合业务网理论及关键技术国家重点实验室 西安 710071) 摘 要：针对 JPEG2000 硬件实现中小波变换与编码之间占用大量存储的问题，该文提出一种基于码块的存储方 案。通过对码块大小片内存储最大程度的复用以及对其高效简单的调度控制，从面积和功耗两方面减小了硬件实现 的开销。在实现中，采用基于行的提升变换结构和比特平面并行的编码方式，提高了效率，确保整个过程的实时处 理。实验结果表明：在实时编码要求下，对分辨率为 512×512 的图像分片进行四级 9/7 或者 5/3 小波分解，码块 大小为 32×32，采用本文结构所用的存储量与直接使用外部存储器的方法相比可减少 80%以上。整个结构已通过 FPGA 验证，且系统时钟可以工作在 100MHz。 关键词：JPEG2000；离散小波变换；EBCOT 算法；低存储；码块 中图分类号：TN402; TN919.81 文献标识码：A 文章编号：1009-5896(2009)03-0731-05 An Efficient DWT-EBCOT Combined VLSI Architecture with Low Memory for JPEG2000 Guo Jie Li Yun-song Wu Cheng-ke Liu Kai Wang Ke-yan (State Key Lab. of Integrated Service Networks, Xidian Univ., Xi’an 710071, China) Abstract: Motivated by an enormous amount of storage between DWT and EBCOT in JPEG2000 hardware implementation, a novel memory-efficient scheme based on code block size is proposed. Further reuse of on-chip code block size memories and efficient scheduling of them reduce hardware cost in both area and power. In the implementation, line-based lifting DWT architecture and bit plane parallel EBCOT design are used. The resulting coding efficiency is improved and the whole architecture can achieve real time processing. Experimental results show that on demand of real time coding, when a tile with resolution up to 512-width and 512-height is decomposed with four levels in 9/7 or 5/3 filters and the size of code block is 32×32, the wavelet coefficients memory n