arm学习经验 uart串口无法正确输出字符.docVIP

UART串口无法正确输出字符 使用.s文件进行初始化设置，程序代码如下： ; Standard definitions of Mode bits and Interrupt (I F) flags in PSRs Mode_USR EQU 0x10 Mode_FIQ EQU 0x11 Mode_IRQ EQU 0x12 Mode_SVC EQU 0x13 Mode_ABT EQU 0x17 Mode_UND EQU 0x1B Mode_SYS EQU 0x1F I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled UND_Stack_Size EQU 0SVC_Stack_Size EQU 0ABT_Stack_Size EQU 0FIQ_Stack_Size EQU 0IRQ_Stack_Size EQU 0USR_Stack_Size EQU 0ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ FIQ_Stack_Size + IRQ_Stack_Size) AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE USR_Stack_Size __initial_sp SPACE ISR_Stack_Size Stack_Top Heap_Size EQU 0 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit ; System Control Unit (SCU) definitions SCU_BASE EQU 0x5C002000 ; SCU Base Address (non-buffered) SCU_CLKCNTR_OFS EQU 0x00 ; Clock Control register Offset SCU_PLLCONF_OFS EQU 0x04 ; PLL Configuration register Offset SCU_SYSSTAT_OFS EQU 0x08 ; System Status Register Offset SCU_PCGR0_OFS EQU 0x14 ; Peripheral Clock Gating Register 0 Offset SCU_PCGR1_OFS EQU 0x18 ; Peripheral Clock Gating Register 1 Offset SCU_PRR0_OFS EQU 0x1C ; Peripheral Reset Register 0 Offset SCU_PRR1_OFS EQU 0x20 ; Peripheral Reset Register 1 Offset SCU_SCR0_OFS EQU 0x34 ; System Configuration Register 0 Offset SCU_PECGR0_OFS EQU 0x2C SCU_PECGR1_OFS EQU 0x30 SCU_GPIOOUT0_OFS EQU 0x44 SCU_GPIOOUT1_OFS EQU 0x48 SCU_GPIOO