【精品文档】关于单片机计算机程序网络安全有关的外文文献翻译：运用物理随机函数设计和实现AEGIS（神盾）单片机安全处理器 4万字符.pdfVIP

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions G. Edward Suh, Charles W. O’Donnell, Ishan Sachdev, and Srinivas Devadas Computer Science and Artificial Intelligence Laboratory (CSAIL) Massachusetts Institute of Technology Cambridge, MA 02139 suh,cwo,isachdev,devadas@ ABSTRACT We will illustrate the benefit of these two environments with ex- Secure processors enable new applications by ensuring private and amples which demonstrate a new class of secure applications. One authentic program execution even in the face of physical attack. such application is a sensor network which monitors environmental conditions. These sensor nodes are vulnerable to physical attack, In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using Physi- and even a single compromised node can propagate fake messages cal Random Functions, we propose a new way of reliably protect- which bring down the entire network. Such attacks are preventable ing and sharing secrets that is more secure than existing solutions if the message passing routines of each node are protected by a based on non-volatile memory. Our architecture gives applications tamper-evident environment. Trusted distributed computing is an- the flexibility of trusting and protecting only a portion of a given other application which is only possible if the remote system is