lect14-连线问题培训课件.ppt

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 14: Wires CMOS VLSI Design CMOS VLSI Design 4th Ed. Lecture 14: Wires 14: Wires * Outline Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters 14: Wires * Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally 14: Wires * Wire Geometry Pitch = w + s Aspect ratio: AR = t/w Old processes had AR 1 Modern processes have AR ? 2 Pack in many skinny wires 14: Wires * Layer Stack AMI 0.6 mm process has 3 metal layers M1 for within-cell routing M2 for vertical routing between cells M3 for horizontal routing between cells Modern processes use 6-10+ metal layers M1: thin, narrow ( 3l) High density cells Mid layers Thicker and wider, (density vs. speed) Top layers: thickest For VDD, GND, clk 14: Wires * Example Intel 90 nm Stack Intel 45 nm Stack [Thompson02] [Moon08] 14: Wires * Interconnect Modeling Current in a wire is analogous to current in a pipe Resistance: narrow size impedes flow Capacitance: trough under the leaky pipe must fill first Inductance: paddle wheel inertia opposes changes in flow rate Negligible for most wires 14: Wires * Lumped Element Models Wires are a distributed system Approximate with lumped element models 3-segment p-model is accurate to 3% in simulation L-model needs 100 segments for same accuracy! Use single segment p-model for Elmore delay 14: Wires * Wire Resistance r = resistivity (W*m) R? = sheet resistance (W/?) ? is a dimensionless unit(!) Count number of squares R = R? * (# of squares) 14: Wires * Choice of Metals Until 180 nm generation, most wires were aluminum Contemporary processes normally use copper Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier Metal Bulk resi