第1章__EDA技术概述.pptVIP

1.基于FPGA嵌入IP硬核的应用。是指在FPGA中预先植入处理器。这使得FPGA灵活的硬件设计与处理器的强大软件功能有机地结合在一起，高效地实现SOPC系统。 2.基于FPGA嵌入IP软核的应用。是指在FPGA中植入软核处理器，如：NIOS II核等。用户可以根据设计的要求，利用相应的EDA工具，对NIOS II及其外围设备进行构建。 3.基于HardCopy技术的应用。是指将成功实现于FPGA器件上的SOPC系统通过特定的技术直接向ASIC转化。把大容量FPGA的灵活性和ASIC的市场优势结合起来，实现对于有较大批量要求并对成本敏感的电子产品，避开了直接设计ASIC的困难。 多数表决器电路符号 Schematic VHDL Description library ieee; use ieee.std_logic_1164.all; entity XYZ is -- 实体 port ( A1, A2, A3 : in std_logic; F : out std_logic ); end XYZ; architecture XYZ _arch of XYZ is begin F = (A1 and A2) or (A2 and A3) or (A1 and A3); end XYZ_arch; VHDL in Quartus Synthesis Fit Simulation Download to Chips * Strategy is to have a very clear delineation of which products compete. Strategy is to make Cyclone IV attractive enough against Spartan-6, but different enough from Cyclone III that customers must reengineer systems to take advantage of the lower cost product. * * Functionality to meet wireless 3G, wireline Access, broadcast converter, industrial Ethernet, consumer imagining requirements Reduce device cost – Smallest density FPGA with transceivers in the industry use 15KLE part instead of 30KLE due to hard PCIe transceivers built from ground up for low cost, not the same as high end transceivers Reduce board/BOM cost – eliminate external transceivers and increase reliability Only 2 power supplies reduce board layer count and cost Low power reduces need for air flow and heat sinks reducing product cost * * * * * Common PCIe bridge chips have list prices between $12 and $20. You can now replace/integrate the PCIe bridge chip in the FPGA for reduced cost and reduced risk of obsolescence. For a complete list of PCIe bridge chips, please take a look at the PCIe Sig integrators list. ASSPs are low cost, limited flexibility and are EOL’d quickly Cyclone IV GX matches cost of ASSPs while providing immense flexibility for infield upgrades, board design simplicity, and ship for a very long ti