计算机体系结构论文Dynamic Warp Subdivision For Integrated Branch and Memory Divergence Tolerance(isca2010).pdfVIP

Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance Jiayuan Meng David Tarjan∗ Kevin Skadron Department of Computer Department of Computer Department of Computer Science Science Science University of Virginia University of Virginia University of Virginia jm6dg@ dtarjan@ skadron@ ABSTRACT observation is becoming important, both because data par- SIMD organizations amortize the area and power of fetch, allelism is common across a wide range of applications; and because data-parallel throughput is increasingly important decode, and issue logic across multiple processing units in or- der to maximize throughput for a given area and power bud- for high performance as single-thread performance improve- ment slows. get. However, throughput is reduced when a set of threads operating in lockstep (a warp) are stalled due to long latency SIMD lockstep operation of multiple datapaths can be im- plemented with vector units, where the SIMD operation is memory accesses. The resulting idle cycles are extremely costly. Multi-threading can hide latencies by interleaving the explicit in the instruction set and a single thread operates on execution of multiple warps, but deep m