vhdl数字逻辑电路设计19例.docVIP

VHDL 数字逻辑电路设计19例 第1章 组合逻辑电路8例 1. 2-4译码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ymq24 IS PORT (EN,A,B:IN STD_LOGIC; YN : OUT STD_LOGIC_vector(3 downto 0 )); END ENTITY ymq24 ; ARCHITECTURE rt1 OF ymq24 IS SIGNAL T:STD_LOGIC_vector(1 downto 0 ); BEGIN T=A B; process(EN,T) begin IF EN=1 THEN YN=1111; ELSIF T=00 THEN YN=1110; ELSIF T=01 THEN YN=1101; ELSIF T=10 THEN YN=1011; ELSE YN=0111; END IF; End process; END ARCHITECTURE rt1; 2. 3-8译码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ymq38 IS PORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC; YN : OUT STD_LOGIC_vector(7 downto 0 )); END ENTITY ymq38 ; ARCHITECTURE rt1 OF ymq38 IS SIGNAL T1,T2:STD_LOGIC_vector(2 downto 0 ); BEGIN T1=A B C; T2=G1 G2N G3N; process(G1,G2N,G3N,T1,T2) begin IF T2/=100 THEN YN ELSIF T1=000 THEN YN ELSIF T1=001 THEN YN ELSIF T1=010 THEN YN ELSIF T1=011 THEN YN ELSIF T1=100 THEN YN ELSIF T1=101 THEN YN ELSIF T1=110 THEN YN ELSE YN END IF; End process; END ARCHITECTURE rt1; 3. 4选1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY xzq41 IS PORT(gn: IN STD_LOGIC; d: IN STD_LOGIC_VECTOR(3 DOWNTO 0); a0,a1: IN STD_LOGIC; y: out STD_LOGIC); END ENTITY xzq41; ARCHITECTURE rt1 OF xzq41 IS signal s: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN S= a1 a0; Process(S,D,gn) begin if gn=0 then CASE (S) IS WHEN 00= Y=d(0); WHEN 01= Y=d(1); WHEN 10= Y=d(2); WHEN 11= Y=d(3); WHEN OTHERS =NULL; END CASE; else y=0; end if; End process; END ARCHITECTURE rt1; 4. 8选1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY xzq81 IS PORT(gn: IN STD_LOGIC; d: IN STD_LOGIC_VECTOR(7 DOWNTO 0); a0,a1,a2: IN STD_LOGIC; y: out STD_LOGIC); EN