数字逻辑课后答案 第五章.docVIP

第五章 习题答案 1. 画出与阵列编程点 解: 2. 画出或阵列编程点 解: 3. 与、或阵列均可编程,画出编程点。 解 ; --- ----X 1X 2X 3X 4 4. 4变量 LUT 编程 解: 5. 用 VHDL 写出 4输入与门 解: 源代码: LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164. ALL ; ENTITY and4 IS PORT (a, b , c , d :IN STD_LOGIC; x :OUT STD_LOGIC ; END and4; ARCHITECTURE and4_arc OF and4 IS BEGIN x =a AND b AND c AND d; END and4_arc; 6. 用 VHDL 写出 4输入或门 解: 源代码: LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164. ALL ; 1 A -B B -F 3 2A 0A 1A 2A 3 SOP 输出 ENTITY or4 IS PORT (a, b , c , d :IN STD_LOGIC; x :OUT STD_LOGIC ; END or4; ARCHITECTURE or4_arc OF or4 IS BEGIN x =a OR b OR c OR d; END or4_arc; 7. 用 VHDL 写出 SOP 表达式 解:源代码: LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164. ALL ; ENTITY sop IS PORT (a, b , c , d , e , f :IN STD_LOGIC; x :OUT STD_LOGIC ; END sop ; ARCHITECTURE sop_arc OF sop IS BEGIN x =(a AND b OR (c AND d OR (e AND f; END sop_arc; 8. 用 VHDL 写出布尔表达式 解:源代码: LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164. ALL ; ENTITY boolean IS PORT (a, b , c :IN STD_LOGIC; f :OUT STD_LOGIC ; END boolean ; ARCHITECTURE boolean_arc OF boolean IS BEGIN f =(a OR (NOT b OR c AND (a OR b OR (NOT c AND ((NOT a OR (NOT b OR (NOT c; END boolean_arc; 9. 用 VHDL 结构法写出 SOP 表达式 解:源代码: ――三输入与非门的逻辑描述 LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164. ALL ; ENTITY nand3 IS PORT (a, b , c :IN STD_LOGIC; x :OUT STD_LOGIC ; END nand3; ARCHITECTURE nand3_arc OF nand3 IS BEGIN x =NOT (a AND b AND c; END nand3_arc; ――顶层结构描述文件 LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164. ALL ; ENTITY sop IS PORT (in1, in2, in3, in4, in5, in6, in7, in8, in9:IN STD_LOGIC; out4:OUT STD_LOGIC; END sop ; ARCHITECTURE sop_arc OF sop IS COMPONENT nand3 PORT (a, b , c :IN STD_LOGIC; x :OUT STD_LOGIC ; END COMPONENT; SIGNAL out1, out2, out3:STD_LOGIC; BEGIN u1:nand3 PORT MAP (in1, in2, in3, out1 ; u2:nand3 PORT MAP (in4, in5, in6, out2 ; u3:nand3 PORT MAP (in7, in8, in9, out3 ; u4:nand3 PORT MAP (out1, out2, out3, out4 ; END sop; 10. 用 VHDL 数据流法写出 SOP 表达式 解:源代码: LIBRARY IEEE ; USE IEEE . STD_LOGIC_1164. ALL ; ENTITY sop IS PORT (in1, in2, in3, in4,