嵌入式开发-嵌入式五级流水线CPU核的设计与实现.docVIP

嵌入式五级流水线CPU核的设计与实现 赖兆磬,潘 明,许 勇,张 辉 (桂林电子科技大学 计算机与控制学院 广西 桂林 541004 摘 要:本文基于FPGA平台设计并实现了一种嵌入式16位RISC CPU核。以MIPS CPU指令集为参考,完成指令集设计;对指令处理过程进行抽象,把指令分成取指、译码、执行、访存、写回五级流水处理,根据处理过程所需要的元件构建五级数据通路;针对流水线处理产生的数据相关构建旁路通路;根据五级数据通路及旁路通路所需要的协调信号构建控制通路;把数据通路和控制通路融合成CPU核。采用VHDL 实现CPU核;在CPU核上运行测试程序,并给出仿真结果;在FPGA平台上对CPU核进行验证。结果表明了所设计CPU核的有效性。 关键词:FPGA;CPU核;数据通路;控制通路 中图分类号:TP332.3 文献标识码:B The Design-implementation of embedded five Stage Pipeline CPU Core LAI Zhao-qing, PAN Ming, XU Yong, ZHANG Hui (School of Computer Science and Control, Guilin University of Electronic Technology, Guilin 541004 , China Abstract: An embedded 16-bit RISC CPU core was designed and implemented on FPGA. Refer to MIPS instruction set, the instruction set was finished; Analyzing the process of each instruction, the process was divided into five stages which is IF, ID, EXE, MEM, WB. Then the five stages data path was constructed according to work unit which is needed in the process; Aim at the data hazard which happens in the pipeline, the forward path was constructed; the control path was constructed according to the data path; the CPU core was composed of data path and control path. The CPU core was implemented with VHDL; the test program was run at the CPU core, then the simulation was presented; the CPU core was verified at FPGA hardware terrace. The result shows that the CPU core is effective. Keywords: FPGA; CPU core; Data path; Control path; 引言 随着微电子技术的迅速发展, 集成电路(ASIC的集成度越来越高。把CPU核、存储器和I/O接口等集成在单一的芯片上,并装载特定操作系统和应用程序,就构成了功能强大的完整的片上系统(System on Chip, SoC[1]。在性能和成本方面,SoC具有传统的板上系统无法比拟的优势,逐渐成为嵌入式系统发展的主流[2]。而CPU核是SoC的核心,如何设计与实现有效的CPU核成为SoC的关键问题。 MIPS(Microprocessor without Interlocked Pipeline Stages是一种优秀的、开放的RISC(Reduced Instruction Set Computer体系结构,在嵌入式系统领域中得到广泛的应用[3],本文选定MIPS体系结构为所设计CPU核的构架。以MIPS CPU的指令集为参考,设计指令集;对指令处理过程进行抽象,可以把指令处理过程进行流水化;为提高CPU核处理的CPI(每条指令的周期数值,同时降低CPU核设计的复杂度,本文把指令分成取指、译码、执行、访存、写回五级流水处理,并根据处理过程所需要的元件构建五级数据通路;采用流水线技术后,由于指令之间的数据相关性会使流水线出现断流现象,为此构建旁路通路解决这个问题;根据五级数据通路及旁路通路所需要的协调信号,构建能使五个处理段同