虚拟FPGA逻辑测试验证平台的设计.docVIP

电子科技大学 硕士学位论文 虚拟FPGA逻辑测试验证平台的设计 姓名:王军 申请学位级别:硕士 专业:测试计量技术及仪器 指导教师:詹惠琴 ABSTRACT AB STRACT an important problem With the rapid development use of the FPGA chip,it is to be considered what to fleetly and exactly connection of the plentiful homotypic FPGA chips.Therefore,the development of the FPGA Logic Test Verification Platform is necessary. This paper mainly discusses the design and realization of a virtual FPGA Logic Test Verification Platform based on the technology of EPP interface and virtual instrument,considered the characteristic of FPGA logic test verification. This paper first summarizes the technology of virtual instrument and introduces the principle of FPGA logic test verification,and secondly introduces the research background and significance of the topic,and then focuses on the collectivity design and implementation of virtual FPGA Logic Test Verification Platform.The following Chapters detailedly discuss the theory and design scheme of the hardware of the instrument,and the functional software design.Finally,the thesis simplely intuoduces the design of the exploitable board of based on FPGA chip and the design of verification examples,and present testing and analyzing result of verification examples. The hardware circuit board is designed and discussed in detail,which consist of the sampling and the logic control unit,storage apparatus, part of test vector generator,data EPP interface,etc.These parts constitute the board,which is provided witll the multi-function of data sampling,vector generating,data memory,timing and counting, data traffic,etc.All control circuits of the instrument are integrated in FPGA. Software is an important component of virtual FPGA Logic Test Verification Platform.Software programming environment is Labwindows/CVI and LabVIEW of NI Company,谢廿1graphical user interface.In software design,the paper uses modular programming and discusses the programming ideas and a detailed explanation of the way,and offers the desig