数字设计基础双语课件（第4章）.pptVIP

4.2 Memory design using gates A logic circuit can maintain a constant output value by the use of feedback whereby the output is connected to the inputs to reinforce the output value. Set-reset memory design ⅰ) R = 0, S = 1, Q = 0; ⅱ) R = 1, S = 0, Q = 1; From the circuit, we can get: Once the output has been forced to a 0 or a 1, the input can return to a 1 and the output will remain unchanged. * 4.2 Memory design using gates It is often convenient to have both a true output Q and a complementary output Q which in normal operation of the memory circuit has the opposite logical value to Q. The memory design shown below is called a latch. The latch can store one binary value, but its outputs will change when one of the inputs changes to a 0. Disadvantage of latch: * 4.2 Memory design using gates Sometimes we have active high inputs memory design. * 4.3 Flip-flops Normally we want the output changes to be synchronized with a clock signal. Such memory designs are called flip-flops. A flip-flop can store a single bit by producing an output of a 0 or a 1 continuously until changed by conditions on the inputs and a clock signal transition. 1. Flip-flop Flip-flops are the basic building block of sequential circuits. There are several types of flip-flops. * 4.3 Flip-flops 2. R-S flip-flop The R-S flip-flop has two inputs, named S and R. S for set, R for reset. （1）Truth table Q+ indicates the value of Q after the activating clock transition. Q- is the value before the clock transition. However, only after a specified clock transition occurs will the outputs take on the required values, before which the outputs can not change even if the S or R inputs change. * 4.3 Flip-flops （2）Characteristic equation Characteristic equation describes the relationship between the Q output and inputs. The characteristic equation of R-S flip-flop is: Q+ = Q R + S （3）Level triggering The simplest form of clock activation is level triggering. When the clock becomes