数字逻辑设计及运用8-3 时序电路的设计 移位计数器.pptVIP

0 1 +5V CLOCK What is the modulo of the circuit below? Answer Key D LD-L C QD QC QB QA 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 Review of last class an MSI 4-bit bidirectional, parallel-in, parallel-out shift register  (4位双向移位寄存器74x194) left-in 左移输入 right-in 右移输入 left means “in the direction from QD to QA,” right means “in the direction from QA to QD.” Function table for the74x194 4-bit universalshift register CLK CLR S1 S0 移 位 寄 存 器 的 扩 展 8.5.3 Shift-Register Counters Serial/parallel conversion is a “data” application, but shift registers have “nondata” applications as well. A shift register can be combined with combinational logic to form a state machine whose state diagram is cyclic. Such a circuit is called a shift-register counter. Unlike a binary counter, a shift-register counter does not count in an ascending or descending binary sequence, but it is useful in many “control” applications. 8.5.5 Shift-Register Counters(移位寄存器计数器) D0 = F ( Q0 , Q1 , … , Qn-1 ) 一般结构： 1000 8.5.6 Ring Counters (环型计数器) D0 D1 D2 D3 —— 非自启动的 无效状态 D0 = Qn-1 self-correcting counter self-correcting counter is designed so that all abnormal states have transitions leading to normal states. Self-correcting counters are desirable for the same reason that we use a minimal-risk approach to state assignment : If something unexpected happens, a counter or state machine should go to a “safe” state. 1000 8.5.6 Ring Counters (环型计数器) —— 非自启动的 无效状态 D0 = Qn-1 self-correcting自启动的,自校正的 Johnson Counter（扭环计数器） D0 = Qn-1’ 0000 有效的状态循环 Shift-Register Counters 一般结构： D0 = F ( Q0 , Q1 , … , Qn-1 ) 环形计数器： 最简单的：D0 = Qn-1 自校正的：D0 = (Qn-2 + … + Q1 + Q0)’ 0111 1011 1101 1110 (Qn-2 · … · Q1 · Q0)’ Q3 Q0 Q2 Q1 Q0 Q1 Q2 Q3 RING COUNTER(P735) The major appeal of a ring counter for control applications is that its sta