基于FPGA的全数字锁相环的设计.docxVIP

PAGE II 摘 要 伴随当下集成电路体系的迅猛发展， 锁相环当下发展为设计集成电路的主要构成 ，基于此研究其具备显著的现实层面的含义。针对传统类型的锁相环而言，其普遍为数模混合电路，工艺层面其同系统芯片之下的数字电路具备兼容层面的问题，基于此构建同数字电路比较兼容的全数字锁相环（ADPLL）具备一定的价值。构建ADPLL 可应用设计数字电路之中的流程，也就是首先编撰了硬件描述语言，此后综合逻辑，基于此对ADPLL具备极强的可进行移植的属性。 该文章在对锁相环基本原理描述过程中，归纳论述了全数字锁相环下的相关优势，可以了解到对全数字锁相环而言 ，其具备很多的优点，出于具备数字的属性，可以很快的对ADPLL进行捕获，基于此对ADPLL而言，特别需要进行分析和研究。 按照分析全数字锁相环，实现了其主子模块的构建和确定，设定了诸多的子模块，即鉴相器子模块、K变模可逆计数器子模块、脉冲加减器子模块和分频器子模块，以及设定关键参数的程序，融合该设计下的仿真波形细致的论述了数字锁相环的工作环节。最终出于QuartusII仿真平台针对锁相环其在FPGA 中落实波形仿真，其证明构建的锁相环，具备优良的性能，可更好的契合预期成效。 关键词：FPGA；锁相环； 子模块；QuartusII；波形仿真 ABSTRACT With the rapid development of the current integrated circuit system, the phase-locked loop has now evolved into the main component of the design of integrated circuits. Based on this research, it has a significant realistic level. For the traditional type of phase-locked loop, it is generally a digital-analog hybrid circuit. At the process level, it has the compatibility level problem with the digital circuit under the system chip. Based on this, an all-digital phase-locked loop compatible with the digital circuit is constructed. ADPLL) has a certain value. The construction of the ADPLL can be applied to the flow of designing digital circuits, that is, the hardware description language is first compiled, and then the integrated logic is based on the extremely portable nature of the ADPLL. In the process of describing the basic principle of the phase-locked loop, this paper summarizes the related advantages under the all-digital phase-locked loop. It can be understood that for the all-digital phase-locked loop, it has many advantages, for the attribute with numbers. The ADPLL can be captured very quickly, based on which analysis and research is particularly needed for the ADPLL. According to the analysis of the all-digital phase-locked loop, the construction and determination of its main sub-module is realized, and many sub-modules are set, namely the phase detector sub-module, the K-module reversible counter sub-mo