王金明——Verilog_HDL_程序设计教程(例子).docVIP

王金明：《Verilog HDL 程序设计教程》【例 3.1】4 位全加器module adder4(cout,sum,ina,inb,cin);output[3:0] sum;output cout;input[3:0] ina,inb;input cin;assign {cout,sum}=ina+inb+cin;endmodule【例 3.2】4 位计数器module count4(out,reset,clk);output[3:0] out;input reset,clk;reg[3:0] out;always @(posedge clk)beginif (reset) out=0; //同步复位else out=out+1; //计数endendmodule【例 3.3】4 位全加器的仿真程序`timescale 1ns/1ns`include adder4.vmodule adder_tp; //测试模块的名字reg[3:0] a,b; //测试输入信号定义为reg 型reg cin;wire[3:0] sum; //测试输出信号定义为wire 型wire cout;integer i,j;adder4 adder(sum,cout,a,b,cin);