EDA半整数分频器课程设计.pdfVIP

实用标准文案 library ieee; use ieee.std_logic_1164.all; entity fpq is port(fsin: in std_logic; Preset :in std_logic_vector(3 downto 0); clk: in std_logic; dout: out std_logic_vector(31 downto 0); seltmp:out std_logic_vector(7 downto 0); smtmp:out std_logic_vector(6 downto 0)); end; architecture art of fpq is component cnt10 port(clk,clr,ena: in std_logic; cq: out std_logic_vector(3 downto 0); carry_out: out std_logic); end component; component reg32b port(load: in std_logic; din: in std_logic_vector(31 downto 0);