2选1数据选择器的VHDL描述.pdfVIP

2选1数据选择器的VHDL描述 ENT ITY mux21a IS PORT( a, b : IN BIT ; s : IN BIT; y : OUT BIT ) ; END ENT ITY mux21a ; ARCHIT ECT URE one OF mux21a IS BEGIN y = a WHEN s = 0 ELSE b ; END ARCHIT ECT URE one ; 译码器的设计 architecture dec_ behave of e1 is signal sel : std_ logic_vector( 0 to 3) ; begin sel(0) = en ; sel(1) = a(0) ; sel(2) = a(1) ; sel(3) = a(2) ; with sel select y = when 1000, when 1001, when 1010,