设计SAR ADC驱动电路,第一部分：ADC工作原理详解.pdfVIP

Designing SAR ADC Drive Circuitry by Rick Downs, Applications Engineering Manager and Miro Oljaca, Systems Engineer Data Acquisition Products, Texas Instruments, Incorporated Part I: A Detailed Look at SAR ADC Operation Designing buffer circuitry for driving successive-approximation (SAR) ADCs requires knowledge of the load that the inputs present. Specifications in data sheets may mislead the user into thinking that analog inputs, for example, are static when in fact they are a very dynamic load. This three-part article will look at the architecture of modern SAR ADCs, and examine the conversion process in detail. In this first part the operation of a modern SAR ADC is discussed. A detailed, step-by-step analysis is then given, illustrating the sampling and conversion process. The final part discusses charge distribution during the sampling process. This analysis will give the user of these devices a better understanding of the inner operations of a charge-redistribution ADC. 1. The SAR ADC Structure S1 20pF 20pF VIN- Buffer Comparator S3 Vmid - Control Data Logic OUT + S4 20pF VIN+ S2 10pF 5pF 5pF VREF S5 S6 Buffer REFIN Fig. 1: Representative SAR Input Stage