EDA技术应用 7.2.4xilinx原版课件 synthesis_8.pptVIP

Synthesis Techniques Objectives Select a proper coding style to create efficient FPGA designs Specify Xilinx resources that need to be instantiated for various FPGA synthesis tools Identify synthesis tool options that can be used to increase performance Describe an approach to using your synthesis tool to obtain higher performance Timing Closure Outline Coding Tips Instantiating Resources Synthesis Options Summary Appendix Inferring Logic and Flip-Flop Resources Inferring Memory Inferring I/Os and Global Resources Simple Coding Steps Yield 3x Performance Use pipeline stages—more bandwidth Use synchronous reset—better system control Use Finite State Machine optimizations Use inferable resources Multiplexer Shift Register LUT (SRL) Block RAM, LUT RAM Cascade DSP Avoid high-level constructs (loops, for example) in code Many synthesis tool produce slow implementations Synthesis Guidelines Use timing constraints Define tight but realistic individual clock constraints Put unrelated clocks into different clock groups Use proper options and attributes Turn off resource sharing Move flip-flops from IOBs closer to logic Turn on FSM optimization Use the retiming option Basic Performance Tips Avoid high-level loop constructs Synthesis tools may not produce optimal results Avoid nested if-then-else statements Most tools implement these in parallel; however, multiple nested if-then-else statements can result in priority encoded logic Use case statements for large decoding Rather than if-then-else Order and group arithmetic and logical functions and operators A = B + C + D + E; should be: A = (B + C) + (D + E) Avoid inadvertent latch inference Cover all possible outputs in every possible branch Easily done by making default assignments before if-then-else and case Targeting Xilinx Some resources must be instantiated or create an IP core (Architecture Wizard and CORE Generator? software) FIFO16, ISERDES, OSERDES, and clock resources Certain resources require specific coding DS