2020年海大_EDA实验1参考答案.docxVIP

Laboratory Exercise 1 Switches, Lights, and Multiplexers ED实验参与答案 Part1 library ieee; use ieee.std_logic_1164.all; entity part1 is port(SW :in std_logic_vector(17 downto 0); LEDR :out std_logic_vector(17 downto 0)); end part1; architecture Behavior of part1 is begin LEDR = SW; end Behavior; part2 library ieee; use ieee.std_logic_1164.all; --a 2 to 1 multiplexer entity entity mux21 is std_logic;:out std_logic); std_logic; :out std_logic); out_m end mux21; --a 2 to 1 multiplexer architecture architecture structural of mux21 is signal u, v : std_logic; begin u = in_x and (not in_s); v = in_y and