EDA技术》实验报告8位二进制加法器设计.docxVIP

EDA 技术》实验报告 实验名称： 8 位二进制全加器设计 姓名： 班级： 学号： 实验日期： 2010-3-29 指导教师： 、实验设计要求 以一位二进制全加器为基本元件，用例化语句写出 8位并行二进制全加器的顶层文件, 并讨论此加法器的电路特性。 、设计原理 电路功能描述 定义了 8位二进制全加器顶层设计元件端口信号， 输入端口： AIN, BIN, 是八 个二进制数，数据类型被定义为 STD_LOGIC_VECTOR。CIN是输入的进位， 数据类型IN STD_LOGIC ;输出端口 ： SUM为和，数据类型IN STD_LOGIC COUT 为输出的进位。 三、实验程序 程序1： 一位二进制全加器设计顶层描述 功能：程序功能简介 VHDL源程序代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY F_ADDER IS PORT (AIN, BIN, CIN : IN STD_LOGIC; COUT, SUM : OUT STD_LOGIC ); END ENTITY F_ADDER; ARCHITECTURE FD1 OF F_ADDER IS COMPONENT H_ADDER IS PORT (A, B : IN STD_LOGIC; CO, SO : OUT STD_LOGIC ); END COMPONENT; SIGNAL D, E, F : STD_LOGIC; BEGIN U1 : H_ADDER PORT MAP(A = AIN, B = BIN, CO = D, SO = E); U2 : H_ADDER PORT MAP(A = E, B = CIN, CO = F, SO = SUM); COUT = D OR F; END ARCHITECTURE FD1; 程序2: 8位并行二进制全加器顶层文件 功能：程序功能简介 VHDL源程序代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY F_ADDER8 IS PORT ( AIN, BIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CIN : IN STD_LOGIC; SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); COUT : OUT STD_LOGIC ); END F_ADDER8; ARCHITECTURE ONE OF F_ADDER8 IS COMPONENT F_ADDER IS PORT (AIN, BIN, CIN : IN STD_LOGIC; COUT, SUM : OUT STD_LOGIC ); END COMPONENT; SIGNAL C1, C2, C3,C4,C5,C6,C7: STD_LOGIC; BEGIN U1 : F_ADDER PORT MAP(AIN = AIN(0), BIN = BIN(0), CIN = CIN, SUM = SUM(0), COUT = C1); U2 : F_ADDER PORT MAP(AIN = AIN(1), BIN = BIN(1), CIN = C1, SUM = SUM(1), COUT = C2); U3 : F_ADDER PORT MAP(AIN = AIN(2), BIN = BIN(2), CIN = C2, SUM = SUM(2), COUT = C3); U4 : F_ADDER PORT MAP(AIN = AIN(3), BIN = BIN(3), CIN = C3, SUM = SUM(3), COUT = C4); U5 : F_ADDER PORT MAP(AIN = AIN(4), BIN = BIN(4), CIN = C4, SUM = SUM(4), COUT = C5); U6 : F_ADDER PORT MAP(AIN = AIN(5), BIN = BIN(5), CIN = C5, SUM = SUM(5), COUT = C6); U7 : F_ADDER PORT MAP(AIN = AIN(6), BIN = BIN(6), CIN = C6, SUM = SUM(6), COUT = C7); U8 : F_ADDER PORT MAP(AIN = AIN(7), BIN = BIN(7), CIN = C7, SUM = SUM(7), COUT = COUT); END ONE; 四、编译及仿真结果 选用器件型号cyclone 编译后使用器件资源情况、引脚配置情况（硬件实验） □ A1HV o □ A1H V o Q] Bill V 0 CIW