模拟集成电路设计流程大纲纲要 .pptVIP

* 共88页 * Spectre –Verilog 数模混合仿真 Push the limit of system performance Reduce parasitic Reduce I/O driving loads Exploit design space between blocks Push the limit of power dissipation Reduce parasitic loads Reduce I/O driving currents Reduce the system size Why Mixed-Signal Simulation? * 共88页 * System in the Real World * 共88页 * Mostly Applied Method of Mixed-Signal Design 系统分成若干个芯片，每个芯片分开设计，再经电路板整合。 * 共88页 * IntegratedMixed-Signal Design * 共88页 * Commercially Available SimulationEnvironments Cadence – ADE：VHDL/Verilog, Verilog-A, Spectre – AMS：VHDL/Veri