编程FPGA的数码管显示Verilog.docVIP

word. word. word. word. word. word. FPGA的数码管显示（Verilog） 按键与数码管显示 module key_led(clk_50M,key,duan_ma,wei_ma); input clk_50M; input [3:0] key; //key为输入的键码的值 output [3:0] wei_ma; output [7:0] duan_ma; wire [3:0] key; reg [7:0] duan_ma; reg [3:0] wei_ma; reg [3:0] key_temp; //设置了一个寄存器 always @ (posedge clk_50M ) begin key_temp=key; //把键码的值赋给寄存器 case ( key_temp ) 4b0111:duan_ma=8b1100_0000; //段码，按键后，数码管显示0 4b1011:duan_ma=8b1001_0000; //段码，数码管显示9 4b1101:duan_ma=8b1000_0010; //段码，数码管显示6 4b1110:duan_ma=8b1011_0000; //段码，数码管显示3 endcase end always @ ( posedge clk_50M ) begin case(