EDA技术应用3.2.2元器件手册ECP3Handbook.pdf

LatticeECP3 Family Handbook HB1009 Version 02.7, February 2011 LatticeECP3 Family Handbook Table of Contents February 2011 Section I. LatticeECP3 Family Data Sheet Introduction Features 1-1 Introduction 1-2 Architecture Architecture Overview 2-1 PFU Blocks 2-2 Slice 2-3 Modes of Operation 2-5 Routing 2-6 sysCLOCK PLLs and DLLs 2-6 General Purpose PLL 2-6 Delay Locked Loops (DLL) 2-7 PLL/DLL Cascading 2-10 PLL/DLL PIO Input Pin Connections 2-10 Clock Dividers 2-10 Clock Distribution Network 2-11 Primary Clock Sources 2-11 Primary Clock Routing 2-13 Dynamic Clock Control (DCC) 2-13 Dynamic Clock Select (DCS) 2-13 Secondary Clock/Control Sources 2-14 Secondary Clock/Control Routing 2-14 Slice Clock Selection 2-16 Edge Clock Sources 2-17 Edge Clock Routing 2-17 sysMEM Memory 2-19 sysMEM Memory Block 2-19 Bus Size Matching 2-19 RAM Initialization and ROM Operation 2-19 Memory Cascading 2-19 Single, Dual and Pseudo-Dual Port Modes 2-20 Memory Core Reset 2-20 sysDSP™ Slice 2-20 sysDSP Slice Approach Compared to General DSP 2-20 LatticeECP3 sysDSP Slice Architecture Features 2-21 MULT DSP Element 2-24 MAC DSP Element 2-25 MMAC DSP Element 2-26 MULTADDSUB DSP Element 2-27 MULTADDSUBSUM DSP Element 2-28 Advanced sysDSP Slice Features 2-29 Cascading 2-29 Addition 2-29