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MachXO2 Family Handbook
HB1010 Version 01.1, January 2011
MachXO2 Family Handbook
Table of Contents
January 2011
Section I. MachXO2 Family Data Sheet
Introduction
Features 1-1
Introduction 1-2
Architecture
Architecture Overview 2-1
PFU Blocks 2-2
Slices 2-3
Modes of Operation 2-4
RAM Mode 2-5
ROM Mode 2-5
Routing 2-5
Clock/Control Distribution Network 2-5
sysCLOCK Phase Locked Loops (PLLs) 2-7
sysMEM Embedded Block RAM Memory 2-9
Programmable I/O Cells (PIC) 2-13
PIO 2-15
Input Register Block 2-15
Output Register Block 2-16
Tri-state Register Block 2-18
Input Gearbox 2-18
Output Gearbox 2-20
DDR Memory Support 2-21
DQS Read Write Block 2-22
sysIO Buffer 2-22
Typical I/O Behavior During Power-up 2-23
Supported Standards 2-23
sysIO Buffer Banks 2-25
Hot Socketing 2-27
On-chip Oscillator 2-27
Embedded Hardened IP Functions and User Flash Memory 2-27
Hardened I2C IP Core 2-28
Hardened SPI IP Core 2-29
Hardened Timer/Counter 2-30
User Flash Memory (UFM) 2-31
Standby Mode and Power Saving Options 2-32
Power On Reset 2-32
Configuration and Testing 2-33
IEEE 1149.1-Compliant Boundary Scan Testability 2-33
Device Configuration 2-33
TraceID 2-34
Density Shifting 2-35
DC and Switching Characteristics
Absolute Maximum Ratings 3-1
Recommended Operating Conditions 3-1
Power Supply Ramp Rates 3-1
Power-On-Reset Voltage Levels 3-2
Programming/Erase Specifications 3-2
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