[22]数字集成电路设计（第二版） digital integrated circuits (2nd edition).pdfVIP

Section 6.2 Static CMOS Design 237 Figure 6.9 shows the simulated low-to-high delay for different input patterns. As expected, the case where both inputs transition go low (A = B = 10) results in a smaller delay, compared to the case where only one input is driven low. Notice that the worst-case low-to-high delay depends upon which input (A or B) goes low. The reason for this involves