中国民航大学CPLD_EDA课程9第9章_VHDL结构与要素.pptxVIP

EDA技术实用教程;;【例9-1】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY andn IS GENERIC ( n : INTEGER ); --定义类属参量及其数据类型 PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);--用类属参量限制矢量长度 c : OUT STD_LOGIC); END; ARCHITECTURE behav OF andn IS BEGIN PROCESS (a) VARIABLE int : STD_LOGIC; BEGIN int := 1; FOR I IN aLENGTH - 1 DOWNTO 0 LOOP IF a(i)=0 THEN int := 0; END IF; END LOOP; c =int ; END PROCESS; END; ;【例9-2】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY exn IS PORT(d1,d2,d3,d4,d5,d6,d7 : IN STD_LOGIC; q1,q2 : OUT STD_LOGIC); END; ARCHITECTURE exn_behav OF exn IS COMPONENT andn --元件调用声明 GENERIC ( n : INTEGER); PORT(a: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); c: OUT STD_LOGIC); END COMPONENT ; BEGIN -- 类属映射语句，定义类属变量，n赋值为2 u1: andn GENERIC MAP (n =2) PORT MAP (a(0)=d1,a(1)=d2,c=q1); u2: andn GENERIC MAP (n =5) -- 定义类属变量，n赋值为5 PORT MAP (a(0)=d3,a(1)=d4,a(2)=d5, a(3)=d6,a(4)=d7, c=q2); END; ;9.1.3 参数传递映射语句;【例9-3】 LIBRARY IEEE; --待例化元件 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY addern IS PORT (a, b: IN STD_LOGIC_VECTOR; result: out STD_LOGIC_VECTOR); END addern; ARCHITECTURE behave OF addern IS BEGIN result = a + b; END; 【例9-4】 LIBRARY IEEE; --顶层设计 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY adders IS GENERIC(msb_operand: INTEGER := 15; msb_sum: INTEGER :=15); PORT(b: IN STD_LOGIC_VECTOR (msb_operand DOWNTO 0); result: OUT STD_LOGIC_VECTOR (msb_sum DOWNTO 0)); END adders; ;ARCHITECTURE behave OF adders IS COMPON