纳米逻辑芯片制造流程.pptVIP

纳米逻辑芯片制造流程;Logic Circuit: 能够 展现 精确的模拟特性，;VDD;基本电路结构：MOS器件结构;18LG adopt 27 Photo mask , if include ESD layer AA/Poly/CT/ M1~M5/ V1~V5 use DUV scanner (13 layer) “ DARC” Cap on Critical layer and Top M6 Poly M1~M5 adopt OPC (optical proximity correction) for line-end shorting island missing Composite Spacer (ONO) PSM method apply on CT layer Cobalt salicide process Low K IMD layer (FSG);Outline;WAFER START RS CHECK P type 8 ~ 12 ohm-cm, non-EPI wafer Start OX 100A dry 1. PR isolation 2. Prevent the laser mark Si recast 3. Surface cleanness 4. Backside oxidati