vhdl_intr设计使用手册.pdfVIP

Introduction to VHDL Course Objectives n Learn the basic constructs of VHDL n Learn the modeling structure of VHDL n Understand the design environments – Simulation – Synthesis Course Outline nVHDL Basics – Overview of language n Design Units – Entity – Architecture – Configurations – Packages (Libraries) nArchitecture Modeling Fundamentals – Signals – Processes • Sequential Statements Course Outline n Understanding VHDL and