4和8位全加器vhdl程序.docx

8 位并行全加器VHDL 源程序： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8 IS PORT(CIN:IN STD_LOGIC; A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); CO:OUT STD_LOGIC); END ENTITY ADDER8; ARCHITECTURE ART OF AD