FPGA可编程逻辑器件芯片XCZU21DR-2FFVD1156I中文规格书.pdfVIP

Introduction to the RocketIO GTX Transceiver Overview The RocketIO™ GTX transceiver is a power-efficient transceiver for Virtex®-5 FPGAs. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications: • Current Mode Logic (CML) serial drivers/buffers with configurable termination, voltage swing, and coupling. • Programmable TX pre-emphasis, RX equalization, and linear and decision feedback equalization (DFE) for optimized signal integrity. • Line rates from 750 Mb/s to 6.5 Gb/s, with optional 5x digital oversampling required for rates between 150 Mb/s and 750 Mb/s. The nominal operation range of the shared PMA PLL is from 1.5 GHz to 3.25 GHz. These are nominal values, see DS202: Virtex-5 FPGA Data Sheet for specifications. • Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channel bonding, and clock correction. • Fixed latency modes for minimized, deterministic datapath latency. • Beacon signaling for PCI Express® designs and Out-of-Band signaling including COM signal support for SATA designs. • RX/TX Gearbox provides header insertion and extraction support for 64B/66B and 64B/67B (Interlaken) protocols. • Receiver eye scan: ♦ Vertical eye scan in the voltage domain for testing purposes