Status_and_plan_of_the_TaichuPix_chip_for_high-rate_CEPC_Ve优秀课件教学rtex_Detector_MOST2_20200220.pptVIP

Status and plan of the TaichuPix chip for the high-rate CEPC Vertex Detector Prepare Meeting for MOST2 Midterm Outline Status of the TaichuPix1 test Status of the TaichuPix2 submission (2nd MPW) Recent design status and plan * Main specs of the full size chip for high rate vertex detector Bunch spacing Higgs: 680ns; W: 210ns; Z: 25ns Meaning 40M/s bunches (same as the ATLAS Vertex) Hit density 2.5hits/bunch/cm2 for Higgs/W; 0.2hits/bunch/cm2 for Z Cluster size: 3pixels/hit Epi- layer thickness：~18μm Pixel size：25μm×25μm * From the CDR of CEPC For Vertex Specs For High rate Vertex Specs For Ladder Prototype Specs Pixel pitch 25μm Hit rate 120MHz/chip Pixel array 512row×1024col TID 1Mrad Date rate 3.84Gbps --triggerless ~110Mbps --trigger Power Density 200mW/cm2 (air cooling) Dead time 500ns --for 98% efficiency Chip size ~1.4cm×2.56cm New proposed architecture by TaichuPix1 Similar to the ATLAS ITK readout architecture: “column-drain” readout Priority based data driven readout Modification: time stamp is added at EOC whenever a new fast-or busy signal is received Dead time: 2 clk for each pixel (50ns @40MHz clk), negligible compared to the average hit rate 2-level FIFO architecture L1 FIFO: In column level, to de-randomize the injecting charge L2 FIFO: Chip level, to match the in/out data rate between the core and interface Trigger readout Make the data rate in a reasonable range Data coincidence by time stamp, only matched event will be readout * From Tianya Wu in User Manual FE-I3-like Pixel ALPIDE-like Pixel First MPW tapeout was submitted in June Thanks IFAE for their tunnel for submission to TJ Chip received in Nov. With 60 chips, 40 chips delivered to China One block area of 5mm×5mm was fully occupied A full functional pixel array (small scale) 85% of the block area A 64×192 Pixel array + Periphery + PLL + Serializer Bias generation included I/O arranged in one edge, as the final chip other independent test blocks (less critical) LDO + PLL We go