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StaticTimingAnalysisforNanometerDesigns
Static Timing Analysis for
Nanometer Designs
A Practical Approach
J. Bhasker ? Rakesh Chadha
Static Timing Analysis for Nanometer Designs
A Practical Approach
J. Bhasker Rakesh Chadha
eSilicon Corporation eSilicon Corporation
1605 N. Cedar Crest Blvd. Suite 615
Allentown, PA 18103, USA
HYPERLINK mailto:jbhasker@ jbhasker@
890 Mountain Ave
New Providence, NJ 07974, USA
HYPERLINK mailto:rchadha@ rchadha@
ISBN 978-0-387-93819-6 e-ISBN 978-0-387-93820-2
DOI: 10.1007/978-0-387-93820-2
Library of Congress Control Number: 2009921502
? Springer Science+Business Media, LLC 2009
All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.
While the advice and information in this book are believed to be true and accurate at the date of going to press, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein.
Some material reprinted from “IEEE Std. 1497-2001, IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process; IEEE Std. 1364-2001, IEEE Standard Verilog Hardware Description Language; IEEE Std.1481-1999, IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System”, with permission from IEEE. The IEEE di
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