Static Timing Analysis for Nanometer Designs详细完整版本.docx

Static Timing Analysis for Nanometer Designs详细完整版本.docx

  1. 1、本文档共587页,可阅读全部内容。
  2. 2、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
StaticTimingAnalysisforNanometerDesigns

Static Timing Analysis for Nanometer Designs A Practical Approach J. Bhasker ? Rakesh Chadha Static Timing Analysis for Nanometer Designs A Practical Approach J. Bhasker Rakesh Chadha eSilicon Corporation eSilicon Corporation 1605 N. Cedar Crest Blvd. Suite 615 Allentown, PA 18103, USA HYPERLINK mailto:jbhasker@ jbhasker@ 890 Mountain Ave New Providence, NJ 07974, USA HYPERLINK mailto:rchadha@ rchadha@ ISBN 978-0-387-93819-6 e-ISBN 978-0-387-93820-2 DOI: 10.1007/978-0-387-93820-2 Library of Congress Control Number: 2009921502 ? Springer Science+Business Media, LLC 2009 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. While the advice and information in this book are believed to be true and accurate at the date of going to press, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Some material reprinted from “IEEE Std. 1497-2001, IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process; IEEE Std. 1364-2001, IEEE Standard Verilog Hardware Description Language; IEEE Std.1481-1999, IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System”, with permission from IEEE. The IEEE di

文档评论(0)

暗伤 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档