MEMORY存储芯片MT46V64M16P-6T IT A中文规格书.pdfVIP

512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 16. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is V . REF 17. Inputs are not recognized as valid until V stabilizes. Once initialized, including self REF refresh mode, VREF must be powered within specified range. Exception: during the period before VREF stabilizes, CKE 0.3 × VDD is recognized as LOW. 18. The output timing reference level, as measured at the timing reference point (indi- cated in Note 3), is V . TT 19. tHZ and tLZ transitions occur in the same access time windows as data valid transi- tions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (High-Z) or begins driving (Low-Z). 20. The intent of the “Don’t Care” state after completion of the postamble is the DQS- driven signal should either be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIH(DC)min) then it must not transition LOW (below VIH(DC) prior to tDQSH [MIN]). 21. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 22. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com- mand. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 23. MIN (tRC o