《EDA技术》学习情境5：多人抢答器的CPLD设计任务.pptVIP

《EDA技术》学习情境5：多人抢答器的CPLD设计任务;简易抢答器的CPLD设计;;VHDL设计初步;原理图输入与 VHDL文本输入设计的区别 Graphic is what you draw is what you get “ tell me what hardware you want and I will give it to you” VHDL is what you write is what functional you get “ tell me how your circuit should behave and the VHDL compiler will give you the hardware that does the job” but the designer can not control how the circuit implement;什么是VHDL？;VHDL的功能和标准;【例5-1】 ENTITY mux21a IS PORT( a, b : IN BIT ; s : IN BIT; y : OUT BIT ) ; END ENTITY mux21a ; ARCHITECTURE one OF mux21a IS BEGIN y = a WHEN s = 0 ELSE b ; END ARCHITECTURE one ;;5.1.1 2选1多路选择器的VHDL描述;5.1.1 2选1多路选择器的VHDL描述;5.1.1 2选1多路选择器的VHDL描述;5.1.2 VHDL相关语句说明;5.1.2 VHDL相关语句说明;5.1.2 VHDL相关语句说明;8. 逻辑操作符AND、OR、NOT;5.1.3 VHDL设计的基本概念和语句小节;5.2 寄存器描述及其VHDL语言现象;比较用4种不同语句的D触发器VHDL程序;用VHDL设计4位计数器;修改后的程序;4位锁存器;用VHDL设计7段16进制译码器;;数据对象：信号Signal 和变量 Variable;例1 四选一多路选择器设计;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS BEGIN process(i0,i1,i2,i3,a,b) variable muxval : integer range 0 to 3; begin muxval := 0; if (a = 1) then muxval := muxval + 1; end if; if (b = 1) then muxval := muxval + 2; end if;;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT (a，b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END ENTITY h_adder； ARCHITECTURE fh1 OF h_adder I BEGIN so = (a OR b)AND(a NAND b); co = NOT( a NAND b); END ARCHITECTURE fh1;;1位二进制全加器;《EDA技术》学习情境5：多人抢答器的CPLD设计任务;5.2.2 D触发器VHDL描述的语言现象说明;2. 设计库和标准程序包;5.2.2 D触发器VHDL描述的语言现象说明;RTL级电路结构;【例5-12】 ENTITY COMP_GOOD IS PORT(a1 : IN BIT; b1 : IN BIT; q1 : OUT BIT ); END ; ARCHITECTURE one OF COMP_GOOD IS BEGIN PROCESS (a1,b1) BEGIN IF a1 b1 THEN q1 = 1 ; ELSE