Verilog测试平台的简介（Testbenches）PPT.ppt

Chapter 15:Introduction to Verilog Testbenches Objectives In this section,you will learn about designing a testbench: Creating clocks Including files Strategic use of tasks and concurrent statements Controlling and observing the design Reporting warnings and errors The Simulation Environment This is a simplified picture of the overall simulation environment. This section concentrates on testbench development strategies. Creating Clocks Example 1 You can define the clock in either the design or its testbench. You can define the clock either behaviorally or structurally. Here are examples of a symmetric clock: Creating Clocks Example 2 Here are examples of a symmetric clock with delayed startup: Creating Clocks Example 3 Here are examples of an asymmetric clock with delayed startup: Designing Your Testbench You can make your testbench as simple or as comolex as you want. A comolex testbench would perform response berifivation “on-the-fly”. Using Include Files Use `include files to ensure project-wide consistency of common source. Using Verilog Tasks Use Verilog tasks in your testbench to encapsulate repeated operations. Using Concurrent Statements Use fork-join blocks in your testbench to concurrently activate parallel tasks. Applying Stimulus Some common stimulus application techniques include: In-line stimulus,applied from an initial block Stimulus applied from a loop or always block Stimulus applied from an array of vectors or integers Stimulus that is recorded during one simulation and played back in another simulation In-Line Stimulus In-line stimulus has the following characteristics: You list the variables only when their values change You can easily define complex timing relationships between signals The testbench can become very long for tests of real designs Stimulus From Loops Stimulus applied from a loop has the following characteristics: For each iteration you assign a new stimulus vector The timing relationships between signals are regular in nature