十进制计数器7段数码管译码器八位数码管扫描显示电路设计.docxVIP

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  • 2022-12-23 发布于广东
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十进制计数器7段数码管译码器八位数码管扫描显示电路设计.docx

实验目的和要求: 进一步熟悉和了解QuartusⅡ的VHDL文本设计流程,以及组合电路的设计仿真和硬件测试。 实验1:根据软件的使用流程,利用QuartusⅡ完成十进制计数器的文本代码编辑输入(ct10)和仿真测试等步骤,并新建波形仿真文件,对十进制计数器进行波形仿真; 实验2:根据所学内容,利用QuartusⅡ完成十六进制7段数码显示译码器的文本代码编辑输入和仿真测试等步骤,给出仿真波形图。 实验3:根据所学知识,完成八位数码管扫描显示电路设计,并完成波形图的仿真。学会该器件的VHDL语言描述,掌握VHDL的语言特点。 实验步骤 1.新建项目 2.编写代码 ①十进制计数器程序如下: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY ct10 IS PORT(CLR:IN STD_LOGIC; CLK:IN STD_LOGIC; CNT:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); END CT10; ARCHITECTURE ART OF CT10 IS BEGIN PROCESS BEGIN WAIT UNTIL CLKEVENT AND CLK=1; IF(CLR=1 OR CNT=9) THEN CNT=0000; ELSE CNT=CNT+1; END IF; END PROCESS; END ART; ②十六进制7段数码显示译码器程序如下: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECL7S IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END; ARCHITECTURE one OF DECL7S IS BEGIN PROCESS( A ) BEGIN CASE A Is WHEN 0000 = LED7S = 0111111; WHEN 0001 = LED7S = 0000110; WHEN 0010 = LED7S = 1011011; WHEN 0011 = LED7S = 1001111; WHEN 0100 = LED7S = 1100110; WHEN 0101 = LED7S = 1101101; WHEN 0110 = LED7S = 1111101; WHEN 0111 = LED7S = 0000111; WHEN 1000 = LED7S = 1111111; WHEN 1001 = LED7S = 1101111; WHEN 1010 = LED7S = 1110111; WHEN 1011 = LED7S = 1111100; WHEN 1100 = LED7S = 0111001; WHEN 1101 = LED7S = 1011110; WHEN 1110 = LED7S = 1111001; WHEN 1111 = LED7S = 1110001; WHEN OTHERS = NULL; END CASE; END PROCESS; END; ③八位数码管扫描显示电路程序: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY scan_led IS PORT ( clk : IN STD_LOGIC; sg : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); bt: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY scan_led; ARCHITECTURE beh OF scan_led IS SIGNAL cnt8 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL q : INTEGER RANGE 0 TO 15; BEGIN P1:PROCESS( cnt8 ) BEGIN CASE cnt8 IS WHEN 000= bt =; q =1; WHEN 001= bt =; q =3; WHEN 010= bt =; q =5; WHEN 011= bt = 00

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